Friday 23 October 2020

ASIC Digital Design Engr, II

Synopsys - Bangalore, Karnataka - Job Description and Requirements 1. SV verification of SERDES / PHY IPs internally developed. Responsibility includes - a. Verification plan development and review. b. Verification environment development. UVM knowledge preferred. c. RTL, GLS & Co-simulations & coverage closure. d. Deliver high quality RTL and other simulation models to customer. e. Verification using internal or 3rd party VIP for the protocol of interest. f. Debug of simulations, including those of real signals modeled using SV for analog. 2. Understand protocols (eg: 25G/50G/100G Ethernet, PON, other networking prot... - Permanent - Full-time

source http://jobviewtrack.com/en-in/job-4f4e416c7e2d2c4e6311530a0f0f6c230c471d1c081f0a6f585e4403016c6311530a0f0f4e220b47066a2d1659425a432f253c27647518505f5657/fd3bcf2e7c84e3de1c41ab7f046b0481.html?affid=aec4b202b3e7b41b

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